1. Field of the Invention
The present invention relates to a display, and more particularly, to a display and a method for controlling same.
2. Description of the Prior Art
Conventionally, a liquid crystal display (LCD) includes a plurality of source drivers, gate drivers, and a timing controller. The timing controller (TCON) is connected to the source drivers to transmit data and control timings. First the gate drivers output a gate signal to activate a gate line, and once the source drivers receive a transfer pulse signal TP from the timing controller, each of the source drivers drives its corresponding data lines, which means that corresponding display voltages are simultaneously supplied to a row of pixels corresponding to the activated gate line in the LCD.
However, there exists gate delays along the activated gate line, due to that each gate lines has parasitic resistors and parasitic capacitors. As can be seen from FIG. 1, corresponding to a first gate line during a first line period t1, the pixels near the gate drivers receive the gate signal with a shape like GS1f, but the pixels at the end of the first gate line receive the gate signal with a shape like GS1e due to the gate delay. After being filtered by the parasitic resistors and parasitic capacitors in the transmission path along the gate line, the shape of the gate signal significantly changes when it arrives at the last pixels in the gate line. Similarly, corresponding to a second gate line during the second line period t2, the pixels near the gate drivers receive the gate signal with a shape like GS2f, but the pixels at the end of the gate line receive the gate signal with a shape like GS2e. It can be seen at the beginning of the second line period t2 that the pixels of the second gate line receives the gate signal GS2 and thus activated, however, the ending pixels of the first gate line may be not fully turned off due to the shape of GS1e, therefore the image quality is affected.
To solve this problem, the pulse width of the gate signals needs to be shortened so that the last pixel in the gate line can be de-activated before the next transfer pulse signal. Shortening the pulse width of the gate signal, however, causes the problem that the charging time of the pixels is also shortened; the pixels may not have enough time to be charged to their target display voltage levels, especially when the panel is operated at high frequency.